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UC T UCT D R OD TE P TE PRO E SOL STITU 4 OB S UB G44Data Sheet IBLE G441, D D OS S
DG201
May 2001 File Number 3115.5
CMOS Quad SPST Analog Switch itle G20 bt MO uad ST aitch utho ) eyrds terrpoion, inctor, itch OS PST, DT, ST, DT, eo, ET, alog itch, anl) rer () OCI
The DG201 solid state analog switch is designed using an improved, high voltage CMOS monolithic technology. It provides ease-of-use and performance advantages not previously available from solid state switches. Destructive latch-up of solid state analog gates have been eliminated by Intersil's CMOS technology. The DG201 is completely specification and pinout compatible with the industry standard devices.
Features
* Switches Greater than 28VP-P Signals with 15V Supplies * Break-Before-Make Switching - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700ns * TTL, DTL, CMOS, PMOS Compatible * Non-Latching with Supply Turn-Off * Complete Monolithic Construction * Industry Standard (DG201)
Part Number Information
PART NUMBER DG201CJ TEMP. RANGE ( oC) 0 to 70 PACKAGE 16 Ld PDIP PKG. NO. E16.3
Applications
* Data Acquisition * Sample and Hold Circuits
Functional Diagram
S
* Operational Amplifier Gain Switching Networks
Pinout
DG201 (PDIP) TOP VIEW
IN1 1 16 IN2 15 D2 14 S2 13 V+(SUBSTRATE) 12 VREF 11 S3 10 D3 9 IN3
IN
N
P
D
D1 2 S1 3 V- 4
DG201 SWITCH CELL
GND 5 S4 6 D4 7
TRUTH TABLE LOGIC 0 1 DG201 ON OFF
IN4 8
SWITCHES SHOWN FOR LOGIC "1" INPUT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright (c) Intersil Americas Inc. 2001
DG201 Functional Diagram
(1/4 DG201)
V+ V-
Q3
Q7 Q5 Q14
Q8 Q1 VREF
Q15 V+ Q10 Q12 Q13
Q2 GATE PROTECTION RESISTOR Q4 Q6
Q9 S1 Q11 D1
INPUT
V-
Pin Descriptions
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL IN1 D1 S1 VGND S4 D4 IN4 IN3 D3 S3 VREF V+ S2 D2 IN2 DESCRIPTION Logic Control for Switch 1 Drain (Output) Terminal for Switch 1 Source (Input) Terminal for Switch 1 Negative Power Supply Terminal Ground Terminal (Logic Common) Source (Input) Terminal for Switch 4 Drain (Output) Terminal for Switch 4 Logic Control for Switch 4 Logic Control for Switch 3 Drain (Output) Terminal for Switch 3 Source (Input) Terminal for Switch 3 Logic Reference Voltage Positive Power Supply Terminal (Substrate) Source (Input) Terminal for Switch 2 Drain (Output) Terminal for Switch 2 Logic Control for Switch 2
2
DG201
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V V+ to VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V VD to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28V VREF to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V VREF to VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Current (Any Terminal). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA ( oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A Maximum Junction Temperature Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range "C" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = 25oC, V+ = +15V, V- = -15V "C" SUFFIX
PARAMETER DYNAMIC CHARACTERISTICS Turn-ON Time (Note 3), tON Turn-OFF Time (Note 3), tOFF Charge Injection, Q Off Isolation Rejection Ratio, OIRR Crosstalk (Channel-to-Channel), CCRR DIGITAL INPUT CHARACTERISTICS Input Logic Current, IIN(ON) Input Logic Current, IN(OFF) ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, r DS(ON) Channel-to-Channel r DS(ON) Match, r DS(ON) Drain OFF Leakage Current, ID(OFF) Source OFF Leakage Current, IS(OFF) Channel ON Leakage Current, ID(ON) + IS(ON) POWER SUPPLY CHARACTERISTICS Supply Current, I+ Positive Supply Current, I- Negative NOTES:
TEST CONDITIONS
0oC
(NOTE 2) 25oC
70oC
UNITS
RL = 1k, VANALOG = -10V to +10V (Figure 1) RL = 1k, VANALOG = -10V to +10V (Figure 1) Figure 2 f = 1MHz, R L = 100, CL 5pF, (Figure 3) One Channel Off
-
1.0 0.5 20 (Typ) 50 (Typ) -50 (Typ)
-
s s mV dB dB
VIN = 0.8V (Note 3) VIN = 2.4V (Note 3)
1 1
1 1
10 10
A A
IS = 10mA, VANALOG = 10V 100 VANALOG = -14V to +14V VANALOG = -14V to +14V VD = VS = -14V to +14V -
15 (Typ) 100 30 (Typ) 5 5 5
125 100 100 200
V nA nA nA
VIN = 0V or VIN = 5V
2000 2000
1000 1000
2000 2000
A A
2. Typical values are for design aid only, not guaranteed and not subject to production testing. 3. All channels are turned off by high "1" logic inputs and all channels are turned on by low "0" inputs; however 0.8V to 2.4V describes the minimum range for switching properly. Peak input current required for transition is typically -120A.
3
DG201 Test Circuits
ANALOG INPUT 10V 3V 0V LOGIC INPUT 10pF VOUT 1k 3V 0V LOGIC INPUT 10nF VOUT ANALOG INPUT 10V
FIGURE 1. t ON AND tOFF TEST CIRCUIT
FIGURE 2. CHARGE INJECTION TEST CIRCUIT
ANALOG INPUT LOGIC INPUT 3V VOUT 100 2VP-P AT 1MHz 51
FIGURE 3. OFF ISOLATION TEST CIRCUIT
V+
Typical Applications
Using the VREF Terminal
The DG201 has an internal voltage divider setting the TTL threshold on the input control lines for V+ equal to +15V. The schematic shown in Figure 4 with nominal resistor values, gives approximately 2.4V on the VREF pin. As the TTL input signal goes from +0.8V to +2.4V, Q 1 and Q 2 switch states to turn the switch ON and OFF. If the power supply voltage is less than +15V, then a resistor (REXT) must be added between V+ and the V REF pin, to restore +2.4V at V REF. The table shows the value of this resistor for various supply voltages, to maintain TTL compatibility. If CMOS logic levels with a +5V supply are being used, the threshold shifts are less critical, but a separate column of suitable values is given in the table. For logic swings of -5V to + 5V, no resistor is needed. In general, the "low" logic level should be <0.8V to prevent Q1 and Q2 from both being ON together (this will cause incorrect switch function).
TABLE 1. V+ SUPPLY (V) +15 +12 +10 +9 +8 +7 REXT FOR TTL LEVELS (k) 420 190 136 98 70 REXT FOR CMOS LEVELS (k) 136 98 70
118k Q1 23k VREF
REXT
Q2 GATE PROTECTION RESISTOR INPUT
FIGURE 4.
4
DG201 Typical Performance Curves
100 DRAIN-SOURCE ON RESISTANCE () V+ = +15V V- = -15V 100 DRAIN-SOURCE ON RESISTANCE () D
125 oC 25 oC
C B 50 A A: B: C: D: 0 -15 -10 V+ = +15V, V- = -15V V+ = +12V, V- = -12V V+ = +10V, V- = -10V V+ = +8V, V- = -8V 10 15
50
-55oC
0 -15
-10
-5 0 5 DRAIN VOLTAGE (V)
10
15
-5 0 5 DRAIN VOLTAGE (V)
FIGURE 5. rDS(ON) vs VD AND TEMPERATURE
CHANNEL ON LEAKAGE CURRENT (nA) 10
FIGURE 6. r DS(ON) vs VD AND POWER SUPPLY VOLTAGE
10 SOURCE OR DRAIN OFF LEAKAGE CURRENT (nA)
1
1
0.1
0.1
0.01 25 45 65 85 TEMPERATURE (oC) 105 125
0.01 25 45 65 85 TEMPERATURE (oC) 105 125
FIGURE 7. ID(ON) vs TEMPERATURE
FIGURE 8. IS(OFF) OR ID(OFF) vs TEMPERATURE
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DG201 Die Characteristics
DIE DIMENSIONS: 94 mils x 101 mils x 14 mils METALLIZATION: Type: Al Thickness: 10kA PASSIVATION: Type: SiO2/Si3N4 SiO2 Thickness: 7kA Si3N4 Thickness: 8kA WORST CASE CURRENT DENSITY: 1 x 105 A/cm2
Metallization Mask Layout
DG201
D1 (2) S1 (3) IN1 (1) IN2 (16) D2 (15) (14) S2
V- (4)
(13) V+ (SUBSTRATE)
GND (5)
(12) VREF
S4 (6) (7) D4 (8) IN4 (9) IN3 (10) D3
(11) S3
BACKSIDE OF CHIP IS V+
6
DG201 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B D1 A1 A2 L A C L E
E16.3 (JEDEC MS-001-BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INCHES SYMBOL A A1 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
-C-
A2 B B1 C D D1 E E1 e eA eB L N
eA eC
C
e
0.010 (0.25) M C A B S
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.300 BSC 0.115 16 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 16
2.93
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